CPU 0: vendor_id = "GenuineIntel" version information (1/eax): processor type = primary processor (0) family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6) model = 0x5 (5) stepping id = 0x4 (4) extended family = 0x0 (0) extended model = 0x5 (5) (simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model) miscellaneous (1/ebx): process local APIC physical ID = 0x0 (0) cpu count = 0x4 (4) CLFLUSH line size = 0x8 (8) brand index = 0x0 (0) brand id = 0x00 (0): unknown feature information (1/edx): x87 FPU on chip = true virtual-8086 mode enhancement = true debugging extensions = true page size extensions = true time stamp counter = true RDMSR and WRMSR support = true physical address extensions = true machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSENTER and SYSEXIT = true memory type range registers = true PTE global bit = true machine check architecture = true conditional move/compare instruction = true page attribute table = true page size extension = true processor serial number = false CLFLUSH instruction = true debug store = false thermal monitor and clock ctrl = false MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true SSE2 extensions = true self snoop = false hyper-threading / multi-core supported = true therm. monitor = false IA64 = false pending break event = false feature information (1/ecx): PNI/SSE3: Prescott New Instructions = true PCLMULDQ instruction = true 64-bit debug store = false MONITOR/MWAIT = false CPL-qualified debug store = false VMX: virtual machine extensions = false SMX: safer mode extensions = false Enhanced Intel SpeedStep Technology = false thermal monitor 2 = false SSSE3 extensions = true context ID: adaptive or shared L1 data = false FMA instruction = true CMPXCHG16B instruction = true xTPR disable = false perfmon and debug = false process context identifiers = true direct cache access = false SSE4.1 extensions = true SSE4.2 extensions = true extended xAPIC support = true MOVBE instruction = true POPCNT instruction = true time stamp counter deadline = true AES instruction = true XSAVE/XSTOR states = true OS-enabled XSAVE/XSTOR = true AVX: advanced vector extensions = true F16C half-precision convert instruction = true RDRAND instruction = true hypervisor guest status = true cache and TLB information (2): 0x4d: L3 cache: 16M, 16-way, 64 byte lines 0x7d: L2 cache: 2M, 8-way, sectored, 64 byte lines 0x30: L1 cache: 32K, 8-way, 64 byte lines 0x2c: L1 data cache: 32K, 8-way, 64 byte lines processor serial number: 0005-0654-0000-0000-0000-0000 deterministic cache parameters (4): --- cache 0 --- cache type = data cache (1) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x7 (7) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 1 --- cache type = instruction cache (2) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x7 (7) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 2 --- cache type = unified cache (3) cache level = 0x2 (2) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0xf (15) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 4095 --- cache 3 --- cache type = unified cache (3) cache level = 0x3 (3) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x3 (3) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0xf (15) ways of associativity = 0x6 (6) WBINVD/INVD behavior on lower caches = false inclusive to lower caches = true complex cache indexing = true number of sets - 1 (s) = 16383 MONITOR/MWAIT (5): smallest monitor-line size (bytes) = 0x0 (0) largest monitor-line size (bytes) = 0x0 (0) enum of Monitor-MWAIT exts supported = true supports intrs as break-event for MWAIT = true number of C0 sub C-states using MWAIT = 0x0 (0) number of C1 sub C-states using MWAIT = 0x0 (0) number of C2 sub C-states using MWAIT = 0x0 (0) number of C3 sub C-states using MWAIT = 0x0 (0) number of C4 sub C-states using MWAIT = 0x0 (0) number of C5 sub C-states using MWAIT = 0x0 (0) number of C6 sub C-states using MWAIT = 0x0 (0) number of C7 sub C-states using MWAIT = 0x0 (0) Thermal and Power Management Features (6): digital thermometer = false Intel Turbo Boost Technology = false ARAT always running APIC timer = true PLN power limit notification = false ECMD extended clock modulation duty = false PTM package thermal management = false HWP base registers = false HWP notification = false HWP activity window = false HWP energy performance preference = false HWP package level request = false HDC base registers = false digital thermometer thresholds = 0x0 (0) ACNT/MCNT supported performance measure = false ACNT2 available = false performance-energy bias capability = false extended feature flags (7): FSGSBASE instructions = true IA32_TSC_ADJUST MSR supported = false SGX: Software Guard Extensions supported = false BMI instruction = true HLE hardware lock elision = true AVX2: advanced vector extensions 2 = true FDP_EXCPTN_ONLY = false SMEP supervisor mode exec protection = true BMI2 instructions = true enhanced REP MOVSB/STOSB = true INVPCID instruction = true RTM: restricted transactional memory = true QM: quality of service monitoring = false deprecated FPU CS/DS = false intel memory protection extensions = false PQE: platform quality of service enforce = false AVX512F: AVX-512 foundation instructions = true AVX512DQ: double & quadword instructions = true RDSEED instruction = true ADX instructions = true SMAP: supervisor mode access prevention = true AVX512IFMA: fused multiply add = false CLFLUSHOPT instruction = false CLWB instruction = true Intel processor trace = false AVX512PF: prefetch instructions = false AVX512ER: exponent & reciprocal instrs = false AVX512CD: conflict detection instrs = true SHA instructions = false AVX512BW: byte & word instructions = true AVX512VL: vector length = true PREFETCHWT1 = false AVX512VBMI: vector byte manipulation = false UMIP: user-mode instruction prevention = false PKU protection keys for user-mode = true OSPKE CR4.PKE and RDPKRU/WRPKRU = true BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0) RDPID: read processor D supported = false SGX_LC: SGX launch config supported = false AVX512_4VNNIW: neural network instrs = false AVX512_4FMAPS: multiply acc single prec = false Direct Cache Access Parameters (9): PLATFORM_DCA_CAP MSR bits = 0 Architecture Performance Monitoring Features (0xa/eax): version ID = 0x0 (0) number of counters per logical processor = 0x0 (0) bit width of counter = 0x0 (0) length of EBX bit vector = 0x0 (0) Architecture Performance Monitoring Features (0xa/ebx): core cycle event not available = false instruction retired event not available = false reference cycles event not available = false last-level cache ref event not available = false last-level cache miss event not avail = false branch inst retired event not available = false branch mispred retired event not avail = false Architecture Performance Monitoring Features (0xa/edx): number of fixed counters = 0x0 (0) bit width of fixed counters = 0x0 (0) x2APIC features / processor topology (0xb): --- level 0 (thread) --- bits to shift APIC ID to get next = 0x0 (0) logical processors at this level = 0x1 (1) level number = 0x0 (0) level type = thread (1) extended APIC ID = 0 --- level 1 (core) --- bits to shift APIC ID to get next = 0x2 (2) logical processors at this level = 0x4 (4) level number = 0x1 (1) level type = core (2) extended APIC ID = 0 XSAVE features (0xd/0): XCR0 lower 32 bits valid bit field mask = 0x000002e7 XCR0 upper 32 bits valid bit field mask = 0x00000000 XCR0 supported: x87 state = true XCR0 supported: SSE state = true XCR0 supported: AVX state = true XCR0 supported: MPX BNDREGS = false XCR0 supported: MPX BNDCSR = false XCR0 supported: AVX-512 opmask = true XCR0 supported: AVX-512 ZMM_Hi256 = true XCR0 supported: AVX-512 Hi16_ZMM = true IA32_XSS supported: PT state = false XCR0 supported: PKRU state = true bytes required by fields in XCR0 = 0x00000a88 (2696) bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696) XSAVE features (0xd/1): XSAVEOPT instruction = true XSAVEC instruction = true XGETBV instruction = true XSAVES/XRSTORS instructions = false SAVE area size in bytes = 0x00000988 (2440) IA32_XSS lower 32 bits valid bit field mask = 0x00000000 IA32_XSS upper 32 bits valid bit field mask = 0x00000000 AVX/YMM features (0xd/2): AVX/YMM save state byte size = 0x00000100 (256) AVX/YMM save state byte offset = 0x00000240 (576) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 opmask features (0xd/5): AVX-512 opmask save state byte size = 0x00000040 (64) AVX-512 opmask save state byte offset = 0x00000440 (1088) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 ZMM_Hi256 features (0xd/6): AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512) AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 Hi16_ZMM features (0xd/7): AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024) AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false PKRU features (0xd/9): PKRU save state byte size = 0x00000008 (8) PKRU save state byte offset = 0x00000a80 (2688) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false hypervisor_id = "KVMKVMKVM " hypervisor features (0x40000001/eax): kvmclock available at MSR 0x11 = true delays unnecessary for PIO ops = true mmu_op = false kvmclock available a MSR 0x4b564d00 = true async pf enable available by MSR = true steal clock supported = false guest EOI optimization enabled = true stable: no guest per-cpu warps expected = true extended feature flags (0x80000001/edx): SYSCALL and SYSRET instructions = true execution disable = true 1-GB large page support = true RDTSCP = true 64-bit extensions technology available = true Intel feature flags (0x80000001/ecx): LAHF/SAHF supported in 64-bit mode = true LZCNT advanced bit manipulation = true 3DNow! PREFETCH/PREFETCHW instructions = true brand = "Intel Xeon Processor (Skylake, IBRS)" L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): instruction # entries = 0xff (255) instruction associativity = 0x1 (1) data # entries = 0xff (255) data associativity = 0x1 (1) L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): instruction # entries = 0xff (255) instruction associativity = 0x1 (1) data # entries = 0xff (255) data associativity = 0x1 (1) L1 data cache information (0x80000005/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x2 (2) size (KB) = 0x40 (64) L1 instruction cache information (0x80000005/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x2 (2) size (KB) = 0x40 (64) L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): instruction # entries = 0x200 (512) instruction associativity = 4-way (4) data # entries = 0x200 (512) data associativity = 4-way (4) L2 unified cache information (0x80000006/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 16-way (8) size (KB) = 0x200 (512) L3 cache information (0x80000006/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 16-way (8) size (in 512KB units) = 0x20 (32) Advanced Power Management Features (0x80000007/edx): temperature sensing diode = false frequency ID (FID) control = false voltage ID (VID) control = false thermal trip (TTP) = false thermal monitor (TM) = false software thermal control (STC) = false 100 MHz multiplier control = false hardware P-State control = false TscInvariant = false Physical Address and Linear Address Size (0x80000008/eax): maximum physical address bits = 0x28 (40) maximum linear (virtual) address bits = 0x30 (48) maximum guest physical address bits = 0x0 (0) Logical CPU cores (0x80000008/ecx): number of CPU cores - 1 = 0x3 (3) ApicIdCoreIdSize = 0x0 (0) (multi-processing synth): multi-core (c=4) (multi-processing method): Intel leaf 0xb (APIC widths synth): CORE_width=2 SMT_width=0 (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0 (synth) = Intel Xeon (unknown model) CPU 1: vendor_id = "GenuineIntel" version information (1/eax): processor type = primary processor (0) family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6) model = 0x5 (5) stepping id = 0x4 (4) extended family = 0x0 (0) extended model = 0x5 (5) (simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model) miscellaneous (1/ebx): process local APIC physical ID = 0x1 (1) cpu count = 0x4 (4) CLFLUSH line size = 0x8 (8) brand index = 0x0 (0) brand id = 0x00 (0): unknown feature information (1/edx): x87 FPU on chip = true virtual-8086 mode enhancement = true debugging extensions = true page size extensions = true time stamp counter = true RDMSR and WRMSR support = true physical address extensions = true machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSENTER and SYSEXIT = true memory type range registers = true PTE global bit = true machine check architecture = true conditional move/compare instruction = true page attribute table = true page size extension = true processor serial number = false CLFLUSH instruction = true debug store = false thermal monitor and clock ctrl = false MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true SSE2 extensions = true self snoop = false hyper-threading / multi-core supported = true therm. monitor = false IA64 = false pending break event = false feature information (1/ecx): PNI/SSE3: Prescott New Instructions = true PCLMULDQ instruction = true 64-bit debug store = false MONITOR/MWAIT = false CPL-qualified debug store = false VMX: virtual machine extensions = false SMX: safer mode extensions = false Enhanced Intel SpeedStep Technology = false thermal monitor 2 = false SSSE3 extensions = true context ID: adaptive or shared L1 data = false FMA instruction = true CMPXCHG16B instruction = true xTPR disable = false perfmon and debug = false process context identifiers = true direct cache access = false SSE4.1 extensions = true SSE4.2 extensions = true extended xAPIC support = true MOVBE instruction = true POPCNT instruction = true time stamp counter deadline = true AES instruction = true XSAVE/XSTOR states = true OS-enabled XSAVE/XSTOR = true AVX: advanced vector extensions = true F16C half-precision convert instruction = true RDRAND instruction = true hypervisor guest status = true cache and TLB information (2): 0x4d: L3 cache: 16M, 16-way, 64 byte lines 0x7d: L2 cache: 2M, 8-way, sectored, 64 byte lines 0x30: L1 cache: 32K, 8-way, 64 byte lines 0x2c: L1 data cache: 32K, 8-way, 64 byte lines processor serial number: 0005-0654-0000-0000-0000-0000 deterministic cache parameters (4): --- cache 0 --- cache type = data cache (1) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x7 (7) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 1 --- cache type = instruction cache (2) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x7 (7) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 2 --- cache type = unified cache (3) cache level = 0x2 (2) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0xf (15) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 4095 --- cache 3 --- cache type = unified cache (3) cache level = 0x3 (3) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x3 (3) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0xf (15) ways of associativity = 0x6 (6) WBINVD/INVD behavior on lower caches = false inclusive to lower caches = true complex cache indexing = true number of sets - 1 (s) = 16383 MONITOR/MWAIT (5): smallest monitor-line size (bytes) = 0x0 (0) largest monitor-line size (bytes) = 0x0 (0) enum of Monitor-MWAIT exts supported = true supports intrs as break-event for MWAIT = true number of C0 sub C-states using MWAIT = 0x0 (0) number of C1 sub C-states using MWAIT = 0x0 (0) number of C2 sub C-states using MWAIT = 0x0 (0) number of C3 sub C-states using MWAIT = 0x0 (0) number of C4 sub C-states using MWAIT = 0x0 (0) number of C5 sub C-states using MWAIT = 0x0 (0) number of C6 sub C-states using MWAIT = 0x0 (0) number of C7 sub C-states using MWAIT = 0x0 (0) Thermal and Power Management Features (6): digital thermometer = false Intel Turbo Boost Technology = false ARAT always running APIC timer = true PLN power limit notification = false ECMD extended clock modulation duty = false PTM package thermal management = false HWP base registers = false HWP notification = false HWP activity window = false HWP energy performance preference = false HWP package level request = false HDC base registers = false digital thermometer thresholds = 0x0 (0) ACNT/MCNT supported performance measure = false ACNT2 available = false performance-energy bias capability = false extended feature flags (7): FSGSBASE instructions = true IA32_TSC_ADJUST MSR supported = false SGX: Software Guard Extensions supported = false BMI instruction = true HLE hardware lock elision = true AVX2: advanced vector extensions 2 = true FDP_EXCPTN_ONLY = false SMEP supervisor mode exec protection = true BMI2 instructions = true enhanced REP MOVSB/STOSB = true INVPCID instruction = true RTM: restricted transactional memory = true QM: quality of service monitoring = false deprecated FPU CS/DS = false intel memory protection extensions = false PQE: platform quality of service enforce = false AVX512F: AVX-512 foundation instructions = true AVX512DQ: double & quadword instructions = true RDSEED instruction = true ADX instructions = true SMAP: supervisor mode access prevention = true AVX512IFMA: fused multiply add = false CLFLUSHOPT instruction = false CLWB instruction = true Intel processor trace = false AVX512PF: prefetch instructions = false AVX512ER: exponent & reciprocal instrs = false AVX512CD: conflict detection instrs = true SHA instructions = false AVX512BW: byte & word instructions = true AVX512VL: vector length = true PREFETCHWT1 = false AVX512VBMI: vector byte manipulation = false UMIP: user-mode instruction prevention = false PKU protection keys for user-mode = true OSPKE CR4.PKE and RDPKRU/WRPKRU = true BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0) RDPID: read processor D supported = false SGX_LC: SGX launch config supported = false AVX512_4VNNIW: neural network instrs = false AVX512_4FMAPS: multiply acc single prec = false Direct Cache Access Parameters (9): PLATFORM_DCA_CAP MSR bits = 0 Architecture Performance Monitoring Features (0xa/eax): version ID = 0x0 (0) number of counters per logical processor = 0x0 (0) bit width of counter = 0x0 (0) length of EBX bit vector = 0x0 (0) Architecture Performance Monitoring Features (0xa/ebx): core cycle event not available = false instruction retired event not available = false reference cycles event not available = false last-level cache ref event not available = false last-level cache miss event not avail = false branch inst retired event not available = false branch mispred retired event not avail = false Architecture Performance Monitoring Features (0xa/edx): number of fixed counters = 0x0 (0) bit width of fixed counters = 0x0 (0) x2APIC features / processor topology (0xb): --- level 0 (thread) --- bits to shift APIC ID to get next = 0x0 (0) logical processors at this level = 0x1 (1) level number = 0x0 (0) level type = thread (1) extended APIC ID = 1 --- level 1 (core) --- bits to shift APIC ID to get next = 0x2 (2) logical processors at this level = 0x4 (4) level number = 0x1 (1) level type = core (2) extended APIC ID = 1 XSAVE features (0xd/0): XCR0 lower 32 bits valid bit field mask = 0x000002e7 XCR0 upper 32 bits valid bit field mask = 0x00000000 XCR0 supported: x87 state = true XCR0 supported: SSE state = true XCR0 supported: AVX state = true XCR0 supported: MPX BNDREGS = false XCR0 supported: MPX BNDCSR = false XCR0 supported: AVX-512 opmask = true XCR0 supported: AVX-512 ZMM_Hi256 = true XCR0 supported: AVX-512 Hi16_ZMM = true IA32_XSS supported: PT state = false XCR0 supported: PKRU state = true bytes required by fields in XCR0 = 0x00000a88 (2696) bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696) XSAVE features (0xd/1): XSAVEOPT instruction = true XSAVEC instruction = true XGETBV instruction = true XSAVES/XRSTORS instructions = false SAVE area size in bytes = 0x00000988 (2440) IA32_XSS lower 32 bits valid bit field mask = 0x00000000 IA32_XSS upper 32 bits valid bit field mask = 0x00000000 AVX/YMM features (0xd/2): AVX/YMM save state byte size = 0x00000100 (256) AVX/YMM save state byte offset = 0x00000240 (576) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 opmask features (0xd/5): AVX-512 opmask save state byte size = 0x00000040 (64) AVX-512 opmask save state byte offset = 0x00000440 (1088) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 ZMM_Hi256 features (0xd/6): AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512) AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 Hi16_ZMM features (0xd/7): AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024) AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false PKRU features (0xd/9): PKRU save state byte size = 0x00000008 (8) PKRU save state byte offset = 0x00000a80 (2688) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false hypervisor_id = "KVMKVMKVM " hypervisor features (0x40000001/eax): kvmclock available at MSR 0x11 = true delays unnecessary for PIO ops = true mmu_op = false kvmclock available a MSR 0x4b564d00 = true async pf enable available by MSR = true steal clock supported = false guest EOI optimization enabled = true stable: no guest per-cpu warps expected = true extended feature flags (0x80000001/edx): SYSCALL and SYSRET instructions = true execution disable = true 1-GB large page support = true RDTSCP = true 64-bit extensions technology available = true Intel feature flags (0x80000001/ecx): LAHF/SAHF supported in 64-bit mode = true LZCNT advanced bit manipulation = true 3DNow! PREFETCH/PREFETCHW instructions = true brand = "Intel Xeon Processor (Skylake, IBRS)" L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): instruction # entries = 0xff (255) instruction associativity = 0x1 (1) data # entries = 0xff (255) data associativity = 0x1 (1) L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): instruction # entries = 0xff (255) instruction associativity = 0x1 (1) data # entries = 0xff (255) data associativity = 0x1 (1) L1 data cache information (0x80000005/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x2 (2) size (KB) = 0x40 (64) L1 instruction cache information (0x80000005/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x2 (2) size (KB) = 0x40 (64) L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): instruction # entries = 0x200 (512) instruction associativity = 4-way (4) data # entries = 0x200 (512) data associativity = 4-way (4) L2 unified cache information (0x80000006/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 16-way (8) size (KB) = 0x200 (512) L3 cache information (0x80000006/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 16-way (8) size (in 512KB units) = 0x20 (32) Advanced Power Management Features (0x80000007/edx): temperature sensing diode = false frequency ID (FID) control = false voltage ID (VID) control = false thermal trip (TTP) = false thermal monitor (TM) = false software thermal control (STC) = false 100 MHz multiplier control = false hardware P-State control = false TscInvariant = false Physical Address and Linear Address Size (0x80000008/eax): maximum physical address bits = 0x28 (40) maximum linear (virtual) address bits = 0x30 (48) maximum guest physical address bits = 0x0 (0) Logical CPU cores (0x80000008/ecx): number of CPU cores - 1 = 0x3 (3) ApicIdCoreIdSize = 0x0 (0) (multi-processing synth): multi-core (c=4) (multi-processing method): Intel leaf 0xb (APIC widths synth): CORE_width=2 SMT_width=0 (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0 (synth) = Intel Xeon (unknown model) CPU 2: vendor_id = "GenuineIntel" version information (1/eax): processor type = primary processor (0) family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6) model = 0x5 (5) stepping id = 0x4 (4) extended family = 0x0 (0) extended model = 0x5 (5) (simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model) miscellaneous (1/ebx): process local APIC physical ID = 0x2 (2) cpu count = 0x4 (4) CLFLUSH line size = 0x8 (8) brand index = 0x0 (0) brand id = 0x00 (0): unknown feature information (1/edx): x87 FPU on chip = true virtual-8086 mode enhancement = true debugging extensions = true page size extensions = true time stamp counter = true RDMSR and WRMSR support = true physical address extensions = true machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSENTER and SYSEXIT = true memory type range registers = true PTE global bit = true machine check architecture = true conditional move/compare instruction = true page attribute table = true page size extension = true processor serial number = false CLFLUSH instruction = true debug store = false thermal monitor and clock ctrl = false MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true SSE2 extensions = true self snoop = false hyper-threading / multi-core supported = true therm. monitor = false IA64 = false pending break event = false feature information (1/ecx): PNI/SSE3: Prescott New Instructions = true PCLMULDQ instruction = true 64-bit debug store = false MONITOR/MWAIT = false CPL-qualified debug store = false VMX: virtual machine extensions = false SMX: safer mode extensions = false Enhanced Intel SpeedStep Technology = false thermal monitor 2 = false SSSE3 extensions = true context ID: adaptive or shared L1 data = false FMA instruction = true CMPXCHG16B instruction = true xTPR disable = false perfmon and debug = false process context identifiers = true direct cache access = false SSE4.1 extensions = true SSE4.2 extensions = true extended xAPIC support = true MOVBE instruction = true POPCNT instruction = true time stamp counter deadline = true AES instruction = true XSAVE/XSTOR states = true OS-enabled XSAVE/XSTOR = true AVX: advanced vector extensions = true F16C half-precision convert instruction = true RDRAND instruction = true hypervisor guest status = true cache and TLB information (2): 0x4d: L3 cache: 16M, 16-way, 64 byte lines 0x7d: L2 cache: 2M, 8-way, sectored, 64 byte lines 0x30: L1 cache: 32K, 8-way, 64 byte lines 0x2c: L1 data cache: 32K, 8-way, 64 byte lines processor serial number: 0005-0654-0000-0000-0000-0000 deterministic cache parameters (4): --- cache 0 --- cache type = data cache (1) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x7 (7) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 1 --- cache type = instruction cache (2) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x7 (7) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 2 --- cache type = unified cache (3) cache level = 0x2 (2) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0xf (15) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 4095 --- cache 3 --- cache type = unified cache (3) cache level = 0x3 (3) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x3 (3) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0xf (15) ways of associativity = 0x6 (6) WBINVD/INVD behavior on lower caches = false inclusive to lower caches = true complex cache indexing = true number of sets - 1 (s) = 16383 MONITOR/MWAIT (5): smallest monitor-line size (bytes) = 0x0 (0) largest monitor-line size (bytes) = 0x0 (0) enum of Monitor-MWAIT exts supported = true supports intrs as break-event for MWAIT = true number of C0 sub C-states using MWAIT = 0x0 (0) number of C1 sub C-states using MWAIT = 0x0 (0) number of C2 sub C-states using MWAIT = 0x0 (0) number of C3 sub C-states using MWAIT = 0x0 (0) number of C4 sub C-states using MWAIT = 0x0 (0) number of C5 sub C-states using MWAIT = 0x0 (0) number of C6 sub C-states using MWAIT = 0x0 (0) number of C7 sub C-states using MWAIT = 0x0 (0) Thermal and Power Management Features (6): digital thermometer = false Intel Turbo Boost Technology = false ARAT always running APIC timer = true PLN power limit notification = false ECMD extended clock modulation duty = false PTM package thermal management = false HWP base registers = false HWP notification = false HWP activity window = false HWP energy performance preference = false HWP package level request = false HDC base registers = false digital thermometer thresholds = 0x0 (0) ACNT/MCNT supported performance measure = false ACNT2 available = false performance-energy bias capability = false extended feature flags (7): FSGSBASE instructions = true IA32_TSC_ADJUST MSR supported = false SGX: Software Guard Extensions supported = false BMI instruction = true HLE hardware lock elision = true AVX2: advanced vector extensions 2 = true FDP_EXCPTN_ONLY = false SMEP supervisor mode exec protection = true BMI2 instructions = true enhanced REP MOVSB/STOSB = true INVPCID instruction = true RTM: restricted transactional memory = true QM: quality of service monitoring = false deprecated FPU CS/DS = false intel memory protection extensions = false PQE: platform quality of service enforce = false AVX512F: AVX-512 foundation instructions = true AVX512DQ: double & quadword instructions = true RDSEED instruction = true ADX instructions = true SMAP: supervisor mode access prevention = true AVX512IFMA: fused multiply add = false CLFLUSHOPT instruction = false CLWB instruction = true Intel processor trace = false AVX512PF: prefetch instructions = false AVX512ER: exponent & reciprocal instrs = false AVX512CD: conflict detection instrs = true SHA instructions = false AVX512BW: byte & word instructions = true AVX512VL: vector length = true PREFETCHWT1 = false AVX512VBMI: vector byte manipulation = false UMIP: user-mode instruction prevention = false PKU protection keys for user-mode = true OSPKE CR4.PKE and RDPKRU/WRPKRU = true BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0) RDPID: read processor D supported = false SGX_LC: SGX launch config supported = false AVX512_4VNNIW: neural network instrs = false AVX512_4FMAPS: multiply acc single prec = false Direct Cache Access Parameters (9): PLATFORM_DCA_CAP MSR bits = 0 Architecture Performance Monitoring Features (0xa/eax): version ID = 0x0 (0) number of counters per logical processor = 0x0 (0) bit width of counter = 0x0 (0) length of EBX bit vector = 0x0 (0) Architecture Performance Monitoring Features (0xa/ebx): core cycle event not available = false instruction retired event not available = false reference cycles event not available = false last-level cache ref event not available = false last-level cache miss event not avail = false branch inst retired event not available = false branch mispred retired event not avail = false Architecture Performance Monitoring Features (0xa/edx): number of fixed counters = 0x0 (0) bit width of fixed counters = 0x0 (0) x2APIC features / processor topology (0xb): --- level 0 (thread) --- bits to shift APIC ID to get next = 0x0 (0) logical processors at this level = 0x1 (1) level number = 0x0 (0) level type = thread (1) extended APIC ID = 2 --- level 1 (core) --- bits to shift APIC ID to get next = 0x2 (2) logical processors at this level = 0x4 (4) level number = 0x1 (1) level type = core (2) extended APIC ID = 2 XSAVE features (0xd/0): XCR0 lower 32 bits valid bit field mask = 0x000002e7 XCR0 upper 32 bits valid bit field mask = 0x00000000 XCR0 supported: x87 state = true XCR0 supported: SSE state = true XCR0 supported: AVX state = true XCR0 supported: MPX BNDREGS = false XCR0 supported: MPX BNDCSR = false XCR0 supported: AVX-512 opmask = true XCR0 supported: AVX-512 ZMM_Hi256 = true XCR0 supported: AVX-512 Hi16_ZMM = true IA32_XSS supported: PT state = false XCR0 supported: PKRU state = true bytes required by fields in XCR0 = 0x00000a88 (2696) bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696) XSAVE features (0xd/1): XSAVEOPT instruction = true XSAVEC instruction = true XGETBV instruction = true XSAVES/XRSTORS instructions = false SAVE area size in bytes = 0x00000988 (2440) IA32_XSS lower 32 bits valid bit field mask = 0x00000000 IA32_XSS upper 32 bits valid bit field mask = 0x00000000 AVX/YMM features (0xd/2): AVX/YMM save state byte size = 0x00000100 (256) AVX/YMM save state byte offset = 0x00000240 (576) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 opmask features (0xd/5): AVX-512 opmask save state byte size = 0x00000040 (64) AVX-512 opmask save state byte offset = 0x00000440 (1088) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 ZMM_Hi256 features (0xd/6): AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512) AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 Hi16_ZMM features (0xd/7): AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024) AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false PKRU features (0xd/9): PKRU save state byte size = 0x00000008 (8) PKRU save state byte offset = 0x00000a80 (2688) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false hypervisor_id = "KVMKVMKVM " hypervisor features (0x40000001/eax): kvmclock available at MSR 0x11 = true delays unnecessary for PIO ops = true mmu_op = false kvmclock available a MSR 0x4b564d00 = true async pf enable available by MSR = true steal clock supported = false guest EOI optimization enabled = true stable: no guest per-cpu warps expected = true extended feature flags (0x80000001/edx): SYSCALL and SYSRET instructions = true execution disable = true 1-GB large page support = true RDTSCP = true 64-bit extensions technology available = true Intel feature flags (0x80000001/ecx): LAHF/SAHF supported in 64-bit mode = true LZCNT advanced bit manipulation = true 3DNow! PREFETCH/PREFETCHW instructions = true brand = "Intel Xeon Processor (Skylake, IBRS)" L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): instruction # entries = 0xff (255) instruction associativity = 0x1 (1) data # entries = 0xff (255) data associativity = 0x1 (1) L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): instruction # entries = 0xff (255) instruction associativity = 0x1 (1) data # entries = 0xff (255) data associativity = 0x1 (1) L1 data cache information (0x80000005/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x2 (2) size (KB) = 0x40 (64) L1 instruction cache information (0x80000005/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x2 (2) size (KB) = 0x40 (64) L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): instruction # entries = 0x200 (512) instruction associativity = 4-way (4) data # entries = 0x200 (512) data associativity = 4-way (4) L2 unified cache information (0x80000006/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 16-way (8) size (KB) = 0x200 (512) L3 cache information (0x80000006/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 16-way (8) size (in 512KB units) = 0x20 (32) Advanced Power Management Features (0x80000007/edx): temperature sensing diode = false frequency ID (FID) control = false voltage ID (VID) control = false thermal trip (TTP) = false thermal monitor (TM) = false software thermal control (STC) = false 100 MHz multiplier control = false hardware P-State control = false TscInvariant = false Physical Address and Linear Address Size (0x80000008/eax): maximum physical address bits = 0x28 (40) maximum linear (virtual) address bits = 0x30 (48) maximum guest physical address bits = 0x0 (0) Logical CPU cores (0x80000008/ecx): number of CPU cores - 1 = 0x3 (3) ApicIdCoreIdSize = 0x0 (0) (multi-processing synth): multi-core (c=4) (multi-processing method): Intel leaf 0xb (APIC widths synth): CORE_width=2 SMT_width=0 (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0 (synth) = Intel Xeon (unknown model) CPU 3: vendor_id = "GenuineIntel" version information (1/eax): processor type = primary processor (0) family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6) model = 0x5 (5) stepping id = 0x4 (4) extended family = 0x0 (0) extended model = 0x5 (5) (simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model) miscellaneous (1/ebx): process local APIC physical ID = 0x3 (3) cpu count = 0x4 (4) CLFLUSH line size = 0x8 (8) brand index = 0x0 (0) brand id = 0x00 (0): unknown feature information (1/edx): x87 FPU on chip = true virtual-8086 mode enhancement = true debugging extensions = true page size extensions = true time stamp counter = true RDMSR and WRMSR support = true physical address extensions = true machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSENTER and SYSEXIT = true memory type range registers = true PTE global bit = true machine check architecture = true conditional move/compare instruction = true page attribute table = true page size extension = true processor serial number = false CLFLUSH instruction = true debug store = false thermal monitor and clock ctrl = false MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true SSE2 extensions = true self snoop = false hyper-threading / multi-core supported = true therm. monitor = false IA64 = false pending break event = false feature information (1/ecx): PNI/SSE3: Prescott New Instructions = true PCLMULDQ instruction = true 64-bit debug store = false MONITOR/MWAIT = false CPL-qualified debug store = false VMX: virtual machine extensions = false SMX: safer mode extensions = false Enhanced Intel SpeedStep Technology = false thermal monitor 2 = false SSSE3 extensions = true context ID: adaptive or shared L1 data = false FMA instruction = true CMPXCHG16B instruction = true xTPR disable = false perfmon and debug = false process context identifiers = true direct cache access = false SSE4.1 extensions = true SSE4.2 extensions = true extended xAPIC support = true MOVBE instruction = true POPCNT instruction = true time stamp counter deadline = true AES instruction = true XSAVE/XSTOR states = true OS-enabled XSAVE/XSTOR = true AVX: advanced vector extensions = true F16C half-precision convert instruction = true RDRAND instruction = true hypervisor guest status = true cache and TLB information (2): 0x4d: L3 cache: 16M, 16-way, 64 byte lines 0x7d: L2 cache: 2M, 8-way, sectored, 64 byte lines 0x30: L1 cache: 32K, 8-way, 64 byte lines 0x2c: L1 data cache: 32K, 8-way, 64 byte lines processor serial number: 0005-0654-0000-0000-0000-0000 deterministic cache parameters (4): --- cache 0 --- cache type = data cache (1) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x7 (7) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 1 --- cache type = instruction cache (2) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0x7 (7) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 63 --- cache 2 --- cache type = unified cache (3) cache level = 0x2 (2) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x0 (0) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0xf (15) ways of associativity = 0x1 (1) WBINVD/INVD behavior on lower caches = true inclusive to lower caches = false complex cache indexing = false number of sets - 1 (s) = 4095 --- cache 3 --- cache type = unified cache (3) cache level = 0x3 (3) self-initializing cache level = true fully associative cache = false extra threads sharing this cache = 0x3 (3) extra processor cores on this die = 0x3 (3) system coherency line size = 0x3f (63) physical line partitions = 0x0 (0) ways of associativity = 0xf (15) ways of associativity = 0x6 (6) WBINVD/INVD behavior on lower caches = false inclusive to lower caches = true complex cache indexing = true number of sets - 1 (s) = 16383 MONITOR/MWAIT (5): smallest monitor-line size (bytes) = 0x0 (0) largest monitor-line size (bytes) = 0x0 (0) enum of Monitor-MWAIT exts supported = true supports intrs as break-event for MWAIT = true number of C0 sub C-states using MWAIT = 0x0 (0) number of C1 sub C-states using MWAIT = 0x0 (0) number of C2 sub C-states using MWAIT = 0x0 (0) number of C3 sub C-states using MWAIT = 0x0 (0) number of C4 sub C-states using MWAIT = 0x0 (0) number of C5 sub C-states using MWAIT = 0x0 (0) number of C6 sub C-states using MWAIT = 0x0 (0) number of C7 sub C-states using MWAIT = 0x0 (0) Thermal and Power Management Features (6): digital thermometer = false Intel Turbo Boost Technology = false ARAT always running APIC timer = true PLN power limit notification = false ECMD extended clock modulation duty = false PTM package thermal management = false HWP base registers = false HWP notification = false HWP activity window = false HWP energy performance preference = false HWP package level request = false HDC base registers = false digital thermometer thresholds = 0x0 (0) ACNT/MCNT supported performance measure = false ACNT2 available = false performance-energy bias capability = false extended feature flags (7): FSGSBASE instructions = true IA32_TSC_ADJUST MSR supported = false SGX: Software Guard Extensions supported = false BMI instruction = true HLE hardware lock elision = true AVX2: advanced vector extensions 2 = true FDP_EXCPTN_ONLY = false SMEP supervisor mode exec protection = true BMI2 instructions = true enhanced REP MOVSB/STOSB = true INVPCID instruction = true RTM: restricted transactional memory = true QM: quality of service monitoring = false deprecated FPU CS/DS = false intel memory protection extensions = false PQE: platform quality of service enforce = false AVX512F: AVX-512 foundation instructions = true AVX512DQ: double & quadword instructions = true RDSEED instruction = true ADX instructions = true SMAP: supervisor mode access prevention = true AVX512IFMA: fused multiply add = false CLFLUSHOPT instruction = false CLWB instruction = true Intel processor trace = false AVX512PF: prefetch instructions = false AVX512ER: exponent & reciprocal instrs = false AVX512CD: conflict detection instrs = true SHA instructions = false AVX512BW: byte & word instructions = true AVX512VL: vector length = true PREFETCHWT1 = false AVX512VBMI: vector byte manipulation = false UMIP: user-mode instruction prevention = false PKU protection keys for user-mode = true OSPKE CR4.PKE and RDPKRU/WRPKRU = true BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0) RDPID: read processor D supported = false SGX_LC: SGX launch config supported = false AVX512_4VNNIW: neural network instrs = false AVX512_4FMAPS: multiply acc single prec = false Direct Cache Access Parameters (9): PLATFORM_DCA_CAP MSR bits = 0 Architecture Performance Monitoring Features (0xa/eax): version ID = 0x0 (0) number of counters per logical processor = 0x0 (0) bit width of counter = 0x0 (0) length of EBX bit vector = 0x0 (0) Architecture Performance Monitoring Features (0xa/ebx): core cycle event not available = false instruction retired event not available = false reference cycles event not available = false last-level cache ref event not available = false last-level cache miss event not avail = false branch inst retired event not available = false branch mispred retired event not avail = false Architecture Performance Monitoring Features (0xa/edx): number of fixed counters = 0x0 (0) bit width of fixed counters = 0x0 (0) x2APIC features / processor topology (0xb): --- level 0 (thread) --- bits to shift APIC ID to get next = 0x0 (0) logical processors at this level = 0x1 (1) level number = 0x0 (0) level type = thread (1) extended APIC ID = 3 --- level 1 (core) --- bits to shift APIC ID to get next = 0x2 (2) logical processors at this level = 0x4 (4) level number = 0x1 (1) level type = core (2) extended APIC ID = 3 XSAVE features (0xd/0): XCR0 lower 32 bits valid bit field mask = 0x000002e7 XCR0 upper 32 bits valid bit field mask = 0x00000000 XCR0 supported: x87 state = true XCR0 supported: SSE state = true XCR0 supported: AVX state = true XCR0 supported: MPX BNDREGS = false XCR0 supported: MPX BNDCSR = false XCR0 supported: AVX-512 opmask = true XCR0 supported: AVX-512 ZMM_Hi256 = true XCR0 supported: AVX-512 Hi16_ZMM = true IA32_XSS supported: PT state = false XCR0 supported: PKRU state = true bytes required by fields in XCR0 = 0x00000a88 (2696) bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696) XSAVE features (0xd/1): XSAVEOPT instruction = true XSAVEC instruction = true XGETBV instruction = true XSAVES/XRSTORS instructions = false SAVE area size in bytes = 0x00000988 (2440) IA32_XSS lower 32 bits valid bit field mask = 0x00000000 IA32_XSS upper 32 bits valid bit field mask = 0x00000000 AVX/YMM features (0xd/2): AVX/YMM save state byte size = 0x00000100 (256) AVX/YMM save state byte offset = 0x00000240 (576) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 opmask features (0xd/5): AVX-512 opmask save state byte size = 0x00000040 (64) AVX-512 opmask save state byte offset = 0x00000440 (1088) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 ZMM_Hi256 features (0xd/6): AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512) AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false AVX-512 Hi16_ZMM features (0xd/7): AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024) AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false PKRU features (0xd/9): PKRU save state byte size = 0x00000008 (8) PKRU save state byte offset = 0x00000a80 (2688) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false hypervisor_id = "KVMKVMKVM " hypervisor features (0x40000001/eax): kvmclock available at MSR 0x11 = true delays unnecessary for PIO ops = true mmu_op = false kvmclock available a MSR 0x4b564d00 = true async pf enable available by MSR = true steal clock supported = false guest EOI optimization enabled = true stable: no guest per-cpu warps expected = true extended feature flags (0x80000001/edx): SYSCALL and SYSRET instructions = true execution disable = true 1-GB large page support = true RDTSCP = true 64-bit extensions technology available = true Intel feature flags (0x80000001/ecx): LAHF/SAHF supported in 64-bit mode = true LZCNT advanced bit manipulation = true 3DNow! PREFETCH/PREFETCHW instructions = true brand = "Intel Xeon Processor (Skylake, IBRS)" L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): instruction # entries = 0xff (255) instruction associativity = 0x1 (1) data # entries = 0xff (255) data associativity = 0x1 (1) L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): instruction # entries = 0xff (255) instruction associativity = 0x1 (1) data # entries = 0xff (255) data associativity = 0x1 (1) L1 data cache information (0x80000005/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x2 (2) size (KB) = 0x40 (64) L1 instruction cache information (0x80000005/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x2 (2) size (KB) = 0x40 (64) L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): instruction # entries = 0x200 (512) instruction associativity = 4-way (4) data # entries = 0x200 (512) data associativity = 4-way (4) L2 unified cache information (0x80000006/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 16-way (8) size (KB) = 0x200 (512) L3 cache information (0x80000006/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 16-way (8) size (in 512KB units) = 0x20 (32) Advanced Power Management Features (0x80000007/edx): temperature sensing diode = false frequency ID (FID) control = false voltage ID (VID) control = false thermal trip (TTP) = false thermal monitor (TM) = false software thermal control (STC) = false 100 MHz multiplier control = false hardware P-State control = false TscInvariant = false Physical Address and Linear Address Size (0x80000008/eax): maximum physical address bits = 0x28 (40) maximum linear (virtual) address bits = 0x30 (48) maximum guest physical address bits = 0x0 (0) Logical CPU cores (0x80000008/ecx): number of CPU cores - 1 = 0x3 (3) ApicIdCoreIdSize = 0x0 (0) (multi-processing synth): multi-core (c=4) (multi-processing method): Intel leaf 0xb (APIC widths synth): CORE_width=2 SMT_width=0 (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0 (synth) = Intel Xeon (unknown model)